Embedded-bridge substrate connectors and methods of assembling same

ABSTRACT

An embedded-bridge substrate connector apparatus includes a patterned reference layer to which a first module and a subsequent module are aligned and the two modules are mated at the patterned reference layer. At least one module includes a silicon bridge connector that bridges to two devices, through the patterned reference layer, to the mated module.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a division of U.S. patent application Ser. No.15/464,920, filed on Mar. 21, 2017, the entire contents of which ishereby incorporated by reference herein.

FIELD

This disclosure relates to embedded-bridge technology for makingsystem-in-package connections.

BACKGROUND

Package miniaturization creates tension between achieving smaller sizewhile achieving increased connection requirements.

BRIEF DESCRIPTION OF THE DRAWINGS

Disclosed embodiments are illustrated by way of example, and not by wayof limitation, in the figures of the accompanying drawings where likereference numerals may refer to similar elements, in which:

FIG. 1A is a cross-section elevation of an embedded-bridge connector ina system-in-package apparatus according to an embodiment;

FIG. 1B is a cross-section elevation of the apparatus depicted in FIG.1A after further processing according to an embodiment;

FIG. 1C is a cross-section elevation of the apparatus depicted in FIG.1B after further processing according to an embodiment;

FIG. 1D is a cross-section elevation of the apparatus depicted in FIG.1C after further processing according to an embodiment;

FIG. 1E is a cross-section elevation of the apparatus depicted in FIG.1D after further processing according to an embodiment;

FIG. 1F is a cross-section elevation of the apparatus depicted in FIG.1E after further processing according to an embodiment;

FIG. 1G is a cross-section elevation of the apparatus depicted in FIG.1F after further processing according to an embodiment;

FIG. 1H is a cross-section elevation of the apparatus depicted in FIG.1G after further processing according to an embodiment;

FIG. 1K is a cross-section 109 of the apparatus depicted in FIG. 1Hafter further processing according to an embodiment. FIGS. 1I and 1J areomitted;

FIG. 1 is a cross-section elevation of the apparatus depicted in FIG. 1Kafter further processing according to an embodiment;

FIG. 1XZ is a detail section taken from FIG. 1 according to anembodiment;

FIG. 2 is a cross-section elevation of an embedded-bridge substrateapparatus according to an embodiment;

FIG. 3 is a process flow diagram that illustrates assembly of anembedded-bridge substrate connector apparatus according to anembodiment; and

FIG. 4 is included to show an example of a higher level deviceapplication for the disclosed embodiments.

DETAILED DESCRIPTION

Disclosed embodiments include self-aligned of devices during assembly ofan embedded-bridge connector apparatus for a system-in-packageapparatus. Embodiments allow a face-to-face die stacking in a bridgingconfiguration of packaged dice. In an embodiment, each die of a secondlayer can be face-to-face connected to at least one die in a first layerof the die package. The layers may be referred to as modules. Theface-to-face connection is also achieved in fine-pitch applications dueto the self-alignment of the package-assembly process embodiments thatuses a reference layer to which each module is mated. Providing areference layer during assembly improves X-Y tolerances. Providing areference layer also improves Z-tolerances as the bridging configurationoverlaps structures that might otherwise need to be multiply stacked.

FIG. 1A is a cross-section elevation of an embedded-bridge connector ina system-in-package apparatus 101 according to an embodiment. Aconductive foil 110 is assembled to a carrier 112 in preparation forpatterning a reference layer. In an embodiment, the carrier 112 includesa release layer 114, a thick copper carrier foil 116, a prepreg layer118, and a core material 120 such as is used for printed circuit boardassembly. In an embodiment, the conductive foil 110 is a coppermaterial.

FIG. 1B is a cross-section elevation 102 of the apparatus 101 depictedin FIG. 1A after further processing according to an embodiment. Apatterned mask 122, such as is used for a plating photoresist, isdisposed on the conductive foil 110 above the carrier 112. The patternedmask 112 may be processed such as by spinning on a photoresist,planarizing, and patterning to open corridors to the conductive foil110.

FIG. 1C is a cross-section elevation 103 of the apparatus 102 depictedin FIG. 1B after further processing according to an embodiment. Areference layer 124 has been plated into the several corridors throughthe patterned mask 122 by using the conductive foil 110 as a platingcathode. In an embodiment, the reference layer 124 is a copper materialthat has been plated by electroplating. In an embodiment, the referencelayer 124 is a copper material that has been plated by electrolessplating. The reference layer 124 is a discrete set of electricallyconductive materials, but it is referred to as “reference layer” 124 asa symmetry of build (or an asymmetry) can be determined from thereference layer 124.

FIG. 1D is a cross-section elevation 104 of the apparatus 103 depictedin FIG. 1C after further processing according to an embodiment. In anembodiment, the patterned mask 122 (see FIG. 1C) has been removed by wetetching that uses a wet-etch chemistry that is selective to leaving thereference layer 124 and the conductive foil 110. In an embodiment, thepatterned mask 122 has been removed by a plasma ash process. It can nowbe seen that the reference layer 124 is a discrete set of conductivematerials that occupy substantially the same Z-directional space.Hereinafter, the reference layer 124 may be referred to also as thepatterned reference layer 124, but in any event, it is represented as adiscrete series of conductive materials that occupy the sameZ-directional space.

FIG. 1E is a cross-section elevation 105 of the apparatus 104 depictedin FIG. 1D after further processing according to an embodiment. A seriesof devices has been assembled to the patterned reference layer 124. Itcan be seen that a first ball-grid array has been assembled to thepatterned reference layer 124, one ball of which is indicated withreference numeral 126. It is seen each ball in the first ball-grid array126 appears at substantially the same elevation in the Z-direction abovethe carrier 112 as determined by assembling the first ball-grid array126 on the reference layer 124. In an embodiment as illustrated in FIG.1D, it can be seen that the first ball-grid array 126 has a uniquepattern that is not necessarily geometrically symmetrical across theapparatus 105, but that it is patterned to connect with a variety ofdevices.

A variety of devices is assembled on the first ball-grid array 126. Inan embodiment, each of the devices is different in Z-height.

In an embodiment, a first device 128 such as a base-band processor 128is accompanied by second device 130. In an embodiment, the second device130 is an integrated passive device 130 such as a balun 130, and it isassembled side-by-side with the first device 128 upon the patternedreference layer 124. In an embodiment, the first device 128, although ithas an intrinsic semiconductive-device application, also hassemiconductive bridge circuitry. Hereinafter, although a device may haveboth an intrinsic semiconductive-device application where designated,and it is used as a semiconductive bridge, it will be referred to ashaving “silicon-bridge” function although other semiconductive materials(e.g. III-V materials) may be used to achieve a semiconductive bridge.

In an embodiment, a third device 132 has silicon-bridge functionality,but it also carries useful semiconductive functionality such as for amemory die 132. Where only the first device 128 and the third device 132are present, the third device 132 may be referred to as a device 132that is adjacent the first device 128.

In an embodiment, a fourth device 134 has both silicon-bridgefunctionality and semiconductive logic functionality such as a processor134. In an embodiment, a subsequent device 136 is provided, and althoughis does not have silicon-bridge functionality (see FIG. 1H), it hasuseful semiconductive functionality such as for a storage memory die136.

FIG. 1F is a cross-section elevation of 106 of the apparatus 105depicted in FIG. 1E after further processing according to an embodiment.A molding compound 138 has been flowed over the several devices 128,130, 132, 134 and 136, and flowing has included underfilling at thepatterned reference layer 124 and the ball-grid array 126 according toan embodiment. After underfilling and capping the molding compound 138under- and above the several devices, processing includes planarizingand trimming the molding compound 138 according to an embodiment. In anembodiment, the molding compound 138 is referred to as a die-sideencapsulation 138.

FIG. 1G is a cross-section elevation of 107 of the apparatus 106depicted in FIG. 1F after further processing according to an embodiment.The apparatus 107 is depicted in positive-X and negative-Z coordinatesas the apparatus 107 has been inverted (compare with FIG. 1F) forfurther processing. The release layer 114, depicted in FIG. 1A, has beenactivated such that the carrier 112 has been removed. Additionally in anembodiment, the conductive foil 110 has also been removed by a polishingprocess that is selective to stopping when the patterned reference layer124 has been exposed. Other removal techniques may be used. Theencapsulated devices that are disposed in the molding compound 138 maybe referred to as a die-side module 140 according to an embodiment.

FIG. 1H is a cross-section elevation of 108 of the apparatus 107depicted in FIG. 1G after further processing according to an embodiment.The apparatus 108 is also depicted in positive-X and negative-Zcoordinates.

Devices embedded in the die-side module 140 have been contacted throughthe reference layer 124 in a self-aligning technique according to anembodiment. In an embodiment, a first printed wiring board (PWB) 142 isdisposed in contact with at least one device. In the illustratedembodiment, the first PWB 142 contacts the first device 128 and thesecond device 130. In an embodiment, a subsequent PWB 144 is in contactwith at least one device. In the illustrated embodiment, the subsequentPWB 144 is in contact with the fourth device 134 and the subsequentdevice 136. In an embodiment, the first PWB 142 and the subsequent PWB144 are a single structure such as a “picture frame” rectangle when theapparatus 108 is observed in plan view. The picture frame designationmay also be referred to as an open-frame where the first PWB 142 and thesubsequent PWB 144 are integral parts of the open-frame structure.

Silicon bridging is accomplished between devices in the die-side module140 and devices that are disposed in about the same Z-coordinate regionthat is taken up by the first- and subsequent PWBs 142 and 144. Thisregion is indicated with reference numeral 146 as a land-side module146.

In an embodiment, a first land-side device 148 contacts the referencelayer 124 and acts as a silicon bridge 148 between the first device 128and the third device 132. In an embodiment beside providingsilicon-bridge functionality, the first land-side device 148 alsoprovides intrinsic logic functionality such as a memory controller.

In an embodiment, a second land-side device 150 contacts the referencelayer 124 and acts as a silicon bridge 150 between the third device 132and the fourth device 134. In an embodiment beside providingsilicon-bridge functionality, the second land-side device 150 alsoprovides intrinsic logic functionality such as an application-specificintegrated circuit (ASIC).

In an embodiment, a subsequent land-side device 152 contacts thereference layer 124 and communicates directly through the referencelayer 124 to the fourth device 134 in the die-side module 140. It can beseen that the fourth device 134 in the die-side module overlaps thesubsequent land-side device 152, and the fourth device 134 also acts asa silicon bridge, which bridges both between the second land-side device150 and the subsequent PWB 144 as well as bridges between the secondland-side device 150 and the subsequent land-side device 152.

Each land-side device is coupled to the patterned reference layer 124through electrical bumps in a second ball-grid array, one bump of whichis indicated with reference numeral 154.

FIG. 1K is a cross-section elevation 109 of the apparatus 108 depictedin FIG. 1H after further processing according to an embodiment. FIGS. 1Iand 1J are omitted. The apparatus 109 is also depicted in positive-X andnegative-Z coordinates. Further processing has been done where aland-side encapsulation 156 has been flowed against the die-sideencapsulation 138. It can be seen that the land-side module 146includes- and is essentially enclosed within the land-side encapsulation156.

FIG. 1 is a cross-section elevation 100 of the apparatus 109 depicted inFIG. 1K after further processing according to an embodiment. Theapparatus 100 has been inverted with respect to FIG. 1K to illustrateboth positive-X and positive-Z coordinates. The die-side module 140 ismated to the land-side module 146 by self-aligning through the referencelayer 124.

Land-side ball arrays are disposed against the first PWB 142 and thesubsequent PWB 144. As can be seen, the land-side module 146 is bumpedwith a land-side ball array, one ball of which is indicated withreference numeral 158 at the first PWB 142. Similarly, a land-side ballarray is bumped on the subsequent PWB 144, one ball of which isindicated with reference numeral 160. Where the respective first andsubsequent PWBs 142 and 144 are unitary such as a picture frame PWB, theland-side ball arrays 158 and 160 are part of the same land-side ballarray.

It can now be understood that an “embedded bridge” is defined as asemiconductive structure that not only provides physical-contactcommunication between two other semiconductive devices, but the embeddedbridge is touched on at least three surfaces by an embedding materialsuch as the molding compound 138. Hence in FIG. 1, three embedded-bridgeinstances are found in first device 128, the third device 132, thefourth device 134 and the subsequent device 136. Thus as also can beseen in FIG. 2, although the third and fourth devices 132 and 134,respectively, are backed by structures 132′ and 134′, respectively,these devices still are each touched by the molding compound 138 onthree surfaces.

FIG. 1XZ is a detail section XZ taken from FIG. 1 according to anembodiment. An uniform asymmetrical ratio exists when measuringcomparative distances, beginning at the center of the reference layer124. Using a symmetry line 162 that bisects the reference layer 124, adie-side distance 124E is taken from the symmetry line 162 to a bond pad164 in the die-side module 140. Similarly using the symmetry line 162, aland-side distance 124A is taken from the symmetry line 162 to a bondpad 166 in the land-side module 146.

It can now be understood that a uniform asymmetry ratio exists in theZ-direction across the symmetry line 162. The uniform asymmetry ratio isbetween any given device in the die-side module 140 that is face-to-faceand that couples with a land-side device in the land-side module 146.This uniform asymmetry ratio exists in an embodiment where bumping sizesmay be different within the respective modules. Measurement of thevarious distances 124E and 124A begin at the symmetry line 162 and endat the respective bond pads where the bond pads 164 and 166 areface-to-face.

Devices of varying thicknesses may be arrayed in the die-side module140. Similarly, devices and PWBs of varying thicknesses may be arrayedin the land-side module 146. Regardless of varying thicknesses ofdevices and PWBs, a uniform asymmetry ratio exists between any twodevices that are vertically proximate and overlapping (face-to-face)across the symmetry line 162. “Vertically proximate and overlapping”means at least part of two devices are face-to-face and electricallycoupled through the reference layer 124. The uniform asymmetry ratio isa comparative distance between any active surface of a device in thedie-side module 140 and an active surface of a land-side device that isface-to-face in the land-side module 146.

For example, the third device 132 is disposed vertically proximate(face-to-face) to the second land-side device 150, and where theiractive surfaces overlap (in the X-direction), there is a die-sidedistance 124E from the symmetry line 162 to the active surface of thethird device 132 (illustrated at the bond pad 164), and there is aland-side distance 124A from the symmetry line 162 to the active surfaceof the second land-side device 150 (illustrated at the bond pad 166).These two distances provide a measurable ratio within the parameters ofassembling an apparatus with packaged devices and optionally withpackaged PWBs. These parameters include fiduciary tolerances in both theX-Y dimensions and in the Z-dimension.

Reference is again made to FIG. 1. To further illustrate the uniformasymmetry ratio, the fourth device 134 is also disposed verticallyproximate (face-to-face) from the second land-side device 150, and wheretheir active surfaces overlap (in the X-direction), there is a die-sidedistance from the symmetry line 162 to the active surface of the thirddevice 132 (illustrated at a bond pad 168) and there is a land-sidedistance from the symmetry line 162 to the active surface of the secondland-side device 150 (illustrated at bond pad 170). These two distancesalso provide a measurable ratio. And the uniform asymmetry ratio can beunderstood that the ratio of distances from the symmetry line 162,between the bond pads 164 and 166 is the same as the ratio of distancesfrom the symmetry line 162, between the bond pads 168 and 170.

To further illustrate, the fourth device 134 is also disposed verticallyproximate (face-to-face) to the third land-side device 152, and wheretheir active surfaces overlap (in the X-direction), there is a die-sidedistance from the symmetry line 162 to the active surface of the fourthdevice 134 (illustrated at a bond pad 172) and a land-side distance fromthe symmetry line 162 to the active surface of the third land-sidedevice 152 (illustrated at a bond pad 174). This means the ratio ofdistances from the symmetry line 162, between the bond pads 164 and 166is the same as the ratio of distances from the symmetry line 162,between the bond pads 172 and 174. Likewise, this means the ratio ofdistances between the bond pads 168 and 170 is the same as the ratio ofdistances between the bond pads 172 and 174.

Reference is again made to FIG. 1XZ. The term “uniformly asymmetrical”can now be understood by the definition of the ratio of distances asdisclosed. To illustrate, the distance from the symmetry line 162 to thebond pad 164 (die-side distance 124E) may be defined as unity, and thedistance from the symmetry line 162 to the bond pad 166 (land-sidedistance 124A) may be defined as twice unity. Consequently, the ratio ofdistances is 0.5:1 and this uniform asymmetry will be measured betweenany two devices that are vertically proximate (face-to-face) in theZ-direction and overlapping in the X-direction.

Reference is again made to FIG. 1. To further illustrate, the distancefrom the symmetry line 162 to the bond pad 172 by definition is unity(as it is the same distance from the symmetry line 162 to the bond pad164), and the distance from the symmetry line 162 to the bond pad 174 ismeasured as twice unity (as it is the same distance from the symmetryline 162 to the bond pad 166). Consequently, the ratio of distances isalso 0.5:1.

FIG. 2 is a cross-section elevation of an embedded-bridge substrateapparatus 200 according to an embodiment. The land side ball arrays 158and 160 contact a board 176 such as a motherboard 176. In an embodiment,the board 176 has an outer surface 178 that acts as an outer shell 178for a computing device.

In an embodiment, the die-side module 140 and the land-side module 146include the board 178 and a power source 180. In an embodiment, thepower source 180 fits between the land-side module 146 and the board176. In an embodiment, the power source 180 fits between the land-sidemodule 146 and the board 176, but it is partially recessed in the board176 (as illustrated). In an embodiment, the power source 180 fitsbetween the land-side module 146 and the board 176, but it is partiallyrecessed in in the land-side encapsulation 156. In an embodiment, thepower source 180 fits between the land-side module 146 and the board176, but it is partially recessed in the board 176 (as illustrated), andit is also partially recessed in in the land-side encapsulation 156.

In an embodiment, a user interface 182 is disposed on the top of thedie-side module 140. In an embodiment, the user interface 182 is atouch-sensitive display 182. Coupling of the user interface 182 to powermay be done by a through-mold via 184 that contacts the board 176.

In an embodiment, heat management is assisted by, e.g., aheat-generating device such as when the fourth device 134 is aprocessor, where a heat sink 134′ backs the fourth device 134, and aportion of the structure 182 acts as a heat exhauster. Similarly in anembodiment, heat management for e.g. a device 132 such asmemory-controller hub 132, is assisted by a heat sink 132′ that backsthe third device 132 and a portion of the structure 182 acts as a heatspreader.

FIG. 3 is a process flow diagram 300 that illustrates assembly of anembedded-bridge substrate connector apparatus according to anembodiment.

At 310, the process includes patterning a mask on a conductive film thatis supported by a carrier.

At 320, the process includes forming a reference layer through acorridor in the patterned mask. The conductive film is used as a cathodeto plate the reference layer.

At 322, the process includes removing the patterned mask. In anembodiment, the mask may be retained as a solder-bump template.

At 330, the process includes attaching a semiconductive device to thereference layer at ball array.

At 340, the process includes encapsulating the semiconductive device,both above the device and underfilling the device.

At 350, the process includes removing the carrier and the conductivefoil. Removal of the carrier and foil result in the die-side module.

At 360, the process includes attaching a land-side device to thedie-side module through the patterned reference layer.

At 362, the process includes attaching at least one printed wiring boardto the die-side module.

At 370, the process includes encapsulating the land-side device and theprinted wiring board, if present, in a land-side encapsulation.

At 380, the process includes assembling the land-side module and thedie-side module to a computing system.

FIG. 4 is included to show an example of a higher level deviceapplication for the disclosed embodiments. The self-alignedembedded-bridge substrate connector embodiments may be found in severalparts of a computing system. In an embodiment, a computing system 400includes, but is not limited to, a desktop computer. In an embodiment, asystem 400 includes, but is not limited to a laptop computer. In anembodiment, a system 400 includes, but is not limited to a netbook. Inan embodiment, a system 400 includes, but is not limited to a tablet. Inan embodiment, a system 400 includes, but is not limited to a notebookcomputer. In an embodiment, a system 400 includes, but is not limited toa personal digital assistant (PDA). In an embodiment, a system 400includes, but is not limited to a server. In an embodiment, a system 400includes, but is not limited to a workstation. In an embodiment, asystem 400 includes, but is not limited to a cellular telephone. In anembodiment, a system 400 includes, but is not limited to a mobilecomputing device. In an embodiment, a system 400 includes, but is notlimited to a smart phone. In an embodiment, a system 400 includes, butis not limited to an internet appliance. Other types of computing devicemay be configured with the microelectronic device that includes anembedded-bridge substrate connector apparatus embodiment.

In an embodiment, the processor 410 has one or more processing cores 412and 412N, where 412N represents the Nth processor core inside processor410 where N is a positive integer. In an embodiment, the electronicdevice system 400 using an embedded-bridge substrate connectorembodiment that includes multiple processors including 410 and 405,where the processor 405 has logic similar or identical to the logic ofthe processor 410. In an embodiment, the processing core 412 includes,but is not limited to, pre-fetch logic to fetch instructions, decodelogic to decode the instructions, execution logic to executeinstructions and the like. In an embodiment, the processor 410 has acache memory 416 to cache at least one of instructions and data for thepower mesh-on-die apparatus in the system 400. The cache memory 416 maybe organized into a hierarchal structure including one or more levels ofcache memory.

In an embodiment, the processor 410 includes a memory controller 414,which is operable to perform functions that enable the processor 410 toaccess and communicate with memory 430 that includes at least one of avolatile memory 432 and a non-volatile memory 434. In an embodiment, theprocessor 410 is coupled with memory 430 and chipset 420. The processor410 may also be coupled to a wireless antenna 478 to communicate withany device configured to at least one of transmit and receive wirelesssignals. In an embodiment, the wireless antenna interface 478 operatesin accordance with, but is not limited to, the IEEE 802.11 standard andits related family, Home Plug AV (HPAV), Ultra Wide Band (UWB),Bluetooth, WiMax, or any form of wireless communication protocol.

In an embodiment, the volatile memory 432 includes, but is not limitedto, Synchronous Dynamic Random Access Memory (SDRAM), Dynamic RandomAccess Memory (DRAM), RAMBUS Dynamic Random Access Memory (RDRAM),and/or any other type of random access memory device. The non-volatilememory 434 includes, but is not limited to, flash memory, phase changememory (PCM), read-only memory (ROM), electrically erasable programmableread-only memory (EEPROM), or any other type of non-volatile memorydevice.

The memory 430 stores information and instructions to be executed by theprocessor 410. In an embodiment, the memory 430 may also store temporaryvariables or other intermediate information while the processor 410 isexecuting instructions. In the illustrated embodiment, the chipset 420connects with processor 410 via Point-to-Point (PtP or P-P) interfaces417 and 422. Either of these PtP embodiments may be achieved using anembedded-bridge substrate connector apparatus embodiment as set forth inthis disclosure. The chipset 420 enables the processor 410 to connect toother elements in the embedded-bridge substrate connector apparatus in asystem 400. In an embodiment, interfaces 417 and 422 operate inaccordance with a PtP communication protocol such as the Intel®QuickPath Interconnect (QPI) or the like. In other embodiments, adifferent interconnect may be used.

In an embodiment, the chipset 420 is operable to communicate with theprocessor 410, 405N, the display device 440, and other devices 472, 476,474, 460, 462, 464, 466, 477, etc. The chipset 420 may also be coupledto a wireless antenna 478 to communicate with any device configured toat least do one of transmit and receive wireless signals.

The chipset 420 connects to the display device 440 via the interface426. The display 440 may be, for example, a liquid crystal display(LCD), a plasma display, cathode ray tube (CRT) display, or any otherform of visual display device. In and embodiment, the processor 410 andthe chipset 420 are merged into an embedded-bridge substrate connectorapparatus in a system. Additionally, the chipset 420 connects to one ormore buses 450 and 455 that interconnect various elements 474, 460, 462,464, and 466. Buses 450 and 455 may be interconnected together via a busbridge 472 such as at least one embedded-bridge substrate connectorapparatus embodiment. In an embodiment, the chipset 420 couples with anon-volatile memory 460, a mass storage device(s) 462, a keyboard/mouse464, and a network interface 466 by way of at least one of the interface424 and 474, the smart TV 476, and the consumer electronics 477, etc.

In and embodiment, the mass storage device 462 includes, but is notlimited to, a solid state drive, a hard disk drive, a universal serialbus flash memory drive, or any other form of computer data storagemedium. In one embodiment, network interface 466 is implemented by anytype of well-known network interface standard including, but not limitedto, an Ethernet interface, a universal serial bus (USB) interface, aPeripheral Component Interconnect (PCI) Express interface, a wirelessinterface and/or any other suitable type of interface. In oneembodiment, the wireless interface operates in accordance with, but isnot limited to, the IEEE 802.11 standard and its related family, HomePlug AV (HPAV), Ultra Wide Band (UWB), Bluetooth, WiMax, or any form ofwireless communication protocol.

While the modules shown in FIG. 4 are depicted as separate blocks withinthe embedded-bridge substrate connector apparatus embodiment in acomputing system 400, the functions performed by some of these blocksmay be integrated within a single semiconductor circuit or may beimplemented using two or more separate integrated circuits. For example,although cache memory 416 is depicted as a separate block withinprocessor 410, cache memory 416 (or selected aspects of 416) can beincorporated into the processor core 412.

Where useful, the computing system 400 may have an outer shell such asthe outer shell 164 depicted in FIG. 2. In an embodiment, an outer shellis an electrically insulated structure that also provides physicalprotection for the embedded-bridge substrate connector apparatusembodiment.

To illustrate the embedded-bridge substrate connector apparatusembodiments and methods disclosed herein, a non-limiting list ofexamples is provided herein:

Example 1 is an embedded-bridge substrate connector apparatuscomprising: a patterned reference layer coupled to a die-side module,the die-side module including a first device and a subsequent deviceencapsulated in the die-side module, wherein each of the first deviceand the subsequent device is electrically coupled to the patternedreference layer; a land-side module coupled to the die-side moduleincluding a land-side device encapsulated in the land-side module andwherein the land-side device is electrically coupled to the first devicethrough the reference layer; and wherein one of the first device and thefirst land-side device is a silicon bridge for electricallycommunicating through the patterned reference layer between an adjacentdevice in one or the other of the die-side module and the land-sidemodule.

In Example 2, the subject matter of Example 1 optionally includes athird device adjacent the first device, wherein the third device iselectrically coupled to the reference layer, and wherein the firstland-side device physically and communicatively bridges between thefirst device and the third device.

In Example 3, the subject matter of any one or more of Examples 1-2optionally include a third device adjacent the first device, wherein thethird device is electrically coupled to the reference layer, and whereinthe first land-side device physically and communicatively bridgesbetween the first device and the third device; and a second deviceopposite the third device and adjacent the first device, wherein thesecond device is electrically coupled through the reference layer to afirst printed wiring board in the land-side module.

In Example 4, the subject matter of any one or more of Examples 1-3optionally include a third device adjacent the first device, wherein thethird device is electrically coupled to the reference layer, and whereinthe first land-side device physically and communicatively bridgesbetween the first device and the third device; a second device oppositethe third device and adjacent the first device, wherein the seconddevice is electrically coupled through the reference layer to a firstprinted wiring board in the land-side module; and wherein the subsequentdevice is coupled through the reference layer to a subsequent printedwiring board in the land-side module.

In Example 5, the subject matter of any one or more of Examples 1-4optionally include a third device adjacent the first device, wherein thethird device is electrically coupled to the reference layer, and whereinthe first land-side device physically and communicatively bridgesbetween the first device and the third device; a second device oppositethe third device and adjacent the first device, wherein the seconddevice is electrically coupled through the reference layer to a firstprinted wiring board in the land-side module; wherein the subsequentdevice is coupled through the reference layer to a subsequent printedwiring board in the land-side module; and a board coupled to the firstprinted wiring board through a land-side ball array.

In Example 6, the subject matter of any one or more of Examples 1-5optionally include a third device adjacent the first device, wherein thethird device is electrically coupled to the reference layer, and whereinthe first land-side device physically and communicatively bridgesbetween the first device and the third device; a second device oppositethe third device and adjacent the first device, wherein the seconddevice is electrically coupled through the reference layer to a firstprinted wiring board in the land-side module; wherein the subsequentdevice is coupled through the reference layer to a subsequent printedwiring board in the land-side module; a board coupled to the firstprinted wiring board through a land-side ball array; and a userinterface coupled to the die-side module and electrically coupled to theboard by a through-mold via.

In Example 7, the subject matter of Example 6 optionally includeswherein the first printed wiring board and the subsequent printed wiringboard are integral parts of the open-frame structure.

In Example 8, the subject matter of any one or more of Examples 2-7optionally include a second device adjacent the first device, whereinthe second device is coupled through the reference layer to a firstprinted wiring board in the land-side module; and a second land-sidedevice in the land-side module, wherein the second land-side device iscoupled through the patterned reference layer to the die-side module.

In Example 9, the subject matter of any one or more of Examples 2-8optionally include a second device adjacent the first device, whereinthe second device is coupled through the reference layer to a firstprinted wiring board in the land-side module; a third device adjacentthe first device, wherein the third device is electrically coupled tothe reference layer, and wherein the first land-side device isphysically and communicatively bridges between the first device and thethird device; and a second land-side device in the land-side module,wherein the second land-side device is coupled through the patternedreference layer to the third device.

In Example 10, the subject matter of any one or more of Examples 2-9optionally include a third device adjacent the first device, wherein thethird device is electrically coupled to the reference layer, and whereinthe first land-side device is physically and communicatively bridgesbetween the first device and the third device; a fourth device adjacentthe third device, wherein the fourth device is electrically coupled tothe reference layer; and a second land-side device in the land-sidemodule, wherein the second land-side device is coupled through thepatterned reference layer to the third device and to the fourth device.

In Example 11, the subject matter of any one or more of Examples 2-10optionally include a third device adjacent the first device, wherein thethird device is electrically coupled to the reference layer, and whereinthe first land-side device is physically and communicatively bridgesbetween the first device and the third device; a fourth device adjacentthe third device, wherein the fourth device is electrically coupled tothe reference layer; a second land-side device in the land-side module,wherein the second land-side device is coupled through the patternedreference layer to the third device and to the fourth device; and athird land-side device disposed in the land-side module and coupledthrough the patterned reference layer to the fourth device, wherein thefourth device overlaps the third land-side device.

Example 12 is a method of assembling an embedded-bridge substrateconnector apparatus, comprising: patterning a mask onto a conductivefoil that is mounted on a carrier; plating a reference layer through acorridor in the mask and on the conductive foil; attaching a firstsemiconductive device to the reference layer at a ball array;encapsulating the first semiconductive device, both above the device andunderfilling the device at the ball array and reference layer, toachieve a die-side module; attaching a land-side first device to thefirst device in the die-side module; and encapsulating the firstland-side device to achieve a land-side module.

In Example 13, the subject matter of Example 12 optionally includesremoving the mask before attaching the first semiconductive device.

In Example 14, the subject matter of any one or more of Examples 12-13optionally include removing the mask; attaching the first device; andattaching a subsequent device to the reference layer.

In Example 15, the subject matter of any one or more of Examples 12-14optionally include removing the mask; attaching the first device;attaching a subsequent device to the reference layer; and attaching athird device to the reference layer, wherein the first land-side devicephysically and communicatively bridges between the first device and thethird device.

In Example 16, the subject matter of any one or more of Examples 12-15optionally include attaching a first printed wiring board to thedie-side module by coupling to the first device.

In Example 17, the subject matter of any one or more of Examples 12-16optionally include attaching a first printed wiring board to thedie-side module by coupling to the first device; and attaching asubsequent printed wiring board to the die-side module by coupling tothe subsequent device.

In Example 18, the subject matter of any one or more of Examples 12-17optionally include attaching a first printed wiring board to thedie-side module by coupling to the first device; and attaching theland-side module to a board through a land-side ball array.

Example 19 is a computing system containing an embedded-bridge substrateconnector apparatus comprising: a patterned reference layer coupled to adie-side module, the die-side module including a first device and asubsequent device encapsulated in the die-side module, wherein each ofthe first device and the subsequent device is electrically coupled tothe patterned reference layer; a land-side module coupled to thedie-side module including a land-side device encapsulated in theland-side module and wherein the land-side device is electricallycoupled to the first device through the reference layer; wherein one ofthe first device and the first land-side device is a silicon bridge forelectrically communicating through the patterned reference layer betweenan adjacent device in one or the other of the die-side module and theland-side module; and a board coupled to the land-side module, whereinthe board includes an electrically insulated outer shell for thecomputing system.

In Example 20, the subject matter of Example 19 optionally includes auser interface that includes a touch-sensitive display.

The above detailed description includes references to the accompanyingdrawings, which form a part of the detailed description. The drawingsshow, by way of illustration, specific embodiments in which theinvention can be practiced. These embodiments are also referred toherein as “examples.” Such examples can include elements in addition tothose shown or described. However, the present inventors alsocontemplate examples in which only those elements shown or described areprovided. Moreover, the present inventors also contemplate examplesusing any combination or permutation of those elements shown ordescribed (or one or more aspects thereof), either with respect to aparticular example (or one or more aspects thereof), or with respect toother examples (or one or more aspects thereof) shown or describedherein.

In the event of inconsistent usages between this document and anydocuments so incorporated by reference, the usage in this documentcontrols.

In this document, the terms “a” or “an” are used, as is common in patentdocuments, to include one or more than one, independent of any otherinstances or usages of “at least one” or “one or more.” In thisdocument, the term “or” is used to refer to a nonexclusive or, such that“A or B” includes “A but not B,” “B but not A,” and “A and B,” unlessotherwise indicated. In this document, the terms “including” and “inwhich” are used as the plain-English equivalents of the respective terms“comprising” and “wherein.” Also, in the following claims, the terms“including” and “comprising” are open-ended, that is, a system, device,article, composition, formulation, or process that includes elements inaddition to those listed after such a term in a claim are still deemedto fall within the scope of that claim. Moreover, in the followingclaims, the terms “first,” “second,” and “third,” etc. are used merelyas labels, and are not intended to impose numerical requirements ontheir objects.

Method examples described herein can be machine or computer-implementedat least in part. Some examples can include a computer-readable mediumor machine-readable medium encoded with instructions operable toconfigure an electrical device to perform methods as described in theabove examples. An implementation of such methods can include code, suchas microcode, assembly language code, a higher-level language code, orthe like. Such code can include computer readable instructions forperforming various methods. The code may form portions of computerprogram products. Further, in an example, the code can be tangiblystored on one or more volatile, non-transitory, or non-volatile tangiblecomputer-readable media, such as during execution or at other times.Examples of these tangible computer-readable media can include, but arenot limited to, hard disks, removable magnetic disks, removable opticaldisks (e.g., compact disks and digital video disks), magnetic cassettes,memory cards or sticks, random access memories (RAMs), read onlymemories (ROMs), and the like.

The above description is intended to be illustrative, and notrestrictive. For example, the above-described examples (or one or moreaspects thereof) may be used in combination with each other. Otherembodiments can be used, such as by one of ordinary skill in the artupon reviewing the above description. The Abstract is provided to complywith 37 C.F.R. § 1.72(b), to allow the reader to quickly ascertain thenature of the technical disclosure. It is submitted with theunderstanding that it will not be used to interpret or limit the scopeor meaning of the claims. Also, in the above Detailed Description,various features may be grouped together to streamline the disclosure.This should not be interpreted as intending that an unclaimed disclosedfeature is essential to any claim. Rather, inventive subject matter maylie in less than all features of a particular disclosed embodiment.Thus, the following claims are hereby incorporated into the DetailedDescription as examples or embodiments, with each claim standing on itsown as a separate embodiment, and it is contemplated that suchembodiments can be combined with each other in various combinations orpermutations. The scope of the invention should be determined withreference to the appended claims, along with the full scope ofequivalents to which such claims are entitled.

1. A method of assembling an embedded-bridge substrate connectorapparatus, comprising: patterning a mask onto a conductive foil that ismounted on a carrier; plating a reference layer through a corridor inthe mask and on the conductive foil; attaching a first semiconductivedevice to the reference layer at a ball array; encapsulating the firstsemiconductive device, both above the device and underfilling the deviceat the ball array and reference layer, to achieve a die-side module;attaching a land-side first device to the first device in the die-sidemodule; and encapsulating the first land-side device to achieve aland-side module.
 2. The method of claim 1, further including removingthe mask before attaching the first semiconductive device.
 3. The methodof claim 1, further including: removing the mask; attaching the firstdevice; and attaching a subsequent device to the reference layer.
 4. Themethod of claim 1, further including: removing the mask; attaching thefirst device; attaching a subsequent device to the reference layer; andattaching a third device to the reference layer, wherein the firstland-side device physically and communicatively bridges between thefirst device and the third device.
 5. The method of claim 1, furtherincluding attaching a first printed wiring board to the die-side moduleby coupling to the first device.
 6. The method of claim 1, furtherincluding: attaching a first printed wiring board to the die-side moduleby coupling to the first device; and attaching a subsequent printedwiring board to the die-side module by coupling to the subsequentdevice.
 7. The method of claim 1, further including: attaching a firstprinted wiring board to the die-side module by coupling to the firstdevice; and attaching the land-side module to a board through aland-side ball array.
 8. A method of fabricating an embedded-bridgesubstrate connector apparatus, the method comprising: forming apatterned reference layer including a die side and a land side, whereinthe patterned reference layer is embedded in and each portion of thepatterned reference layer is exposed by a die-side encapsulation,wherein the patterned reference layer is coupled to a die-side module,the die-side module including a first device and a subsequent deviceencapsulated in the die-side encapsulation, wherein each of the firstdevice and the subsequent device is electrically coupled to thepatterned reference layer; coupling a land-side module to the die-sidemodule, the land-side module including a first land-side deviceencapsulated in a land-side encapsulation and wherein the firstland-side device is electrically coupled to the first device through thepatterned reference layer, wherein the patterned reference layer iscontacted by electrical bumps on the die side and by electrical bumps onthe land side, wherein a first one of the electrical bumps contacts apatterned reference layer element and the first device, and wherein asecond one of the electrical bumps contacts the patterned referencelayer element and the first land-side device; and wherein one of thefirst device and the first land-side device is a silicon bridge forelectrically communicating through the patterned reference layer betweenan adjacent device in one or the other of the die-side module and theland-side module.
 9. The method of claim 8, further including: couplinga third device to the patterned reference layer, the third deviceadjacent the first device, wherein the third device is electricallycoupled to the patterned reference layer, and wherein the firstland-side device physically and communicatively bridges between thefirst device and the third device.
 10. The method of claim 8, furtherincluding: coupling a third device to the patterned reference layer, thethird device adjacent the first device, wherein the third device iselectrically coupled to the patterned reference layer, and wherein thefirst land-side device physically and communicatively bridges betweenthe first device and the third device; and coupling a second device tothe patterned reference layer, the second device opposite the thirddevice and adjacent the first device, wherein the second device iselectrically coupled through the patterned reference layer to a firstprinted wiring board in the land-side module.
 11. The method of claim 8,further including: coupling a third device to the patterned referencelayer, the third device adjacent the first device, wherein the thirddevice is electrically coupled to the patterned reference layer, andwherein the first land-side device physically and communicativelybridges between the first device and the third device; coupling a seconddevice to the patterned reference layer, the second device opposite thethird device and adjacent the first device, wherein the second device iselectrically coupled through the patterned reference layer to a firstprinted wiring board in the land-side module; and wherein the subsequentdevice is coupled through the patterned reference layer to a subsequentprinted wiring board in the land-side module.
 12. The method of claim 8,further including: coupling a third device to the patterned referencelayer, the third device adjacent the first device, wherein the thirddevice is electrically coupled to the patterned reference layer, andwherein the first land-side device physically and communicativelybridges between the first device and the third device; coupling a seconddevice to the patterned reference layer, the second device opposite thethird device and adjacent the first device, wherein the second device iselectrically coupled through the patterned reference layer to a firstprinted wiring board in the land-side module; wherein the subsequentdevice is coupled through the patterned reference layer to a subsequentprinted wiring board in the land-side module; and coupling a board tothe first printed wiring board through a land-side ball array.
 13. Themethod of claim 8, further including: coupling a third device to thepatterned reference layer, the third device adjacent the first device,wherein the third device is electrically coupled to the patternedreference layer, and wherein the first land-side device physically andcommunicatively bridges between the first device and the third device;coupling a second device to the patterned reference layer, the seconddevice opposite the third device and adjacent the first device, whereinthe second device is electrically coupled through the patternedreference layer to a first printed wiring board in the land-side module;wherein the subsequent device is coupled through the patterned referencelayer to a subsequent printed wiring board in the land-side module;coupling a board to the first printed wiring board through a land-sideball array; and coupling a user interface to the die-side module andelectrically coupled to the board by a through-mold via.
 14. The methodof claim 13, wherein the first printed wiring board and the subsequentprinted wiring board are integral parts of an open-frame structure. 15.The method of claim 9, further including: coupling a second device tothe patterned reference layer, the second device adjacent the firstdevice, wherein the second device is coupled through the patternedreference layer to a first printed wiring board in the land-side module;and coupling a second land-side device to the patterned reference layer,the second land-side device in the land-side module, wherein the secondland-side device is coupled through the patterned reference layer to thedie-side module.
 16. The method of claim 9, further including: couplinga second device to the patterned reference layer, the second deviceadjacent the first device, wherein the second device is coupled throughthe patterned reference layer to a first printed wiring board in theland-side module; and coupling a second land-side device to thepatterned reference layer, the second land-side device in the land-sidemodule, wherein the second land-side device is coupled through thepatterned reference layer to the third device.
 17. The method of claim9, further including: coupling a fourth device to the patternedreference layer, the fourth device adjacent the third device, whereinthe fourth device is electrically coupled to the patterned referencelayer; and coupling a second land-side device to the patterned referencelayer, the second land-side device in the land-side module, wherein thesecond land-side device is coupled through the patterned reference layerto the third device and to the fourth device.
 18. The method of claim 9,further including: coupling a fourth device to the patterned referencelayer, the fourth device adjacent the third device, wherein the fourthdevice is electrically coupled to the patterned reference layer;coupling a second land-side device to the patterned reference layer, thesecond land-side device in the land-side module, wherein the secondland-side device is coupled through the patterned reference layer to thethird device and to the fourth device; and coupling a third land-sidedevice to the patterned reference layer, the third land-side devicedisposed in the land-side module and coupled through the patternedreference layer to the fourth device, wherein the fourth device overlapsthe third land-side device.